Memory testing apparatuses for testing various types of semiconductor memories including, for example, a memory (IC memory) constructed by a semiconductor integrated circuit (IC) can be classified, roughly, into a memory testing apparatus for testing a memory in wafer state before packaged and a memory testing apparatus for testing a memory after packaged. The memory testing apparatus for testing a memory in wafer state before packaged differs remarkably from the memory testing apparatus for testing a memory after packaged in that the former apparatus is provided with a failure repair processing function or means that decides whether a failure memory cell or cells existing in a memory having redundancy structure described later on can be repaired or not.
In recent years, a semiconductor memory (particularly, an IC memory) has a tendency that its storage capacity is increased and that its size is miniaturized, and with the increased memory capacity and the miniaturization, a defect rate of IC memories has been increased. In order to lower the defect rate of IC memories, in other words, in order to prevent the yield of IC memories from being decreased, there has been manufactured, for example, an IC memory in which a failure memory cell or cells detected therein can be electrically replaced with a spare memory cell or cells (called a spare line, a repair line or a redundancy circuit in this technical field). An IC memory of this type that has a spare memory cell or cells (hereinafter, referred to as spare line) formed therein is called a memory having redundancy structure in this technical field, and analysis as to whether a repair of a failure memory cell or cells existing in this memory of redundancy structure can be effected or not is carried out in a failure repair analyzing and processing apparatus.
A prior memory testing apparatus provided with a failure repair analyzing and processing apparatus of this type is shown in FIG. 4 in a block diagram by a rough construction thereof. This memory testing apparatus TES comprises, roughly speaking, a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a driver 116, an analog level comparator (hereinafter, referred to as comparator) 117, a failure analysis memory 118, a failure repair analyzing and processing apparatus 119, a logical amplitude reference voltage source 121, a comparison reference voltage source 122, and a device power source 123. Further, in the following description, a case of testing an IC memory in wafer state before packaged will be described. However, in cases of testing various kinds of semiconductor memories in wafer state before packaged in addition to IC memories, testing thereof will be carried out in the same manner.
The main controller 111 is generally constituted of a computer system and a test program PM created by a user (programmer) is previously loaded therein. This main controller 111 controls the whole of the memory testing apparatus in accordance with the test program PM. The main controller 111 is connected, via a tester bus TBUS, to the pattern generator 112, the timing generator 113, the waveform formatter 114, the logical comparator 115, the failure analysis memory 118, the failure repair analyzing and processing apparatus 119, the logical amplitude reference voltage source 121, the comparison reference voltage source 122, the device power source 123, and the like.
An IC memory to be tested (memory under test) 200 is formed into a semiconductor wafer WH in this example. Before testing of the memory under test 200 is started, various kinds of data are, at first, set from the main controller 111. The pattern generator 112 supplies test pattern data to the waveform formatter 114 in accordance with the test program PM. On the other hand, the timing generator 113 generates timing signals (clock pulses) for controlling operation timings of the waveform formatter 114, the logical comparator 115, and the like.
The waveform formatter 114 converts the test pattern data supplied from the pattern generator 112 into a test pattern signal having a real waveform. This test pattern signal is applied to the memory under test 200 via the driver 116 which in turn amplifies in voltage the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source 121. The test pattern signal is stored in a memory cell of the memory under test 200, that has an address specified by an address signal, and the storage content is read out therefrom in a read cycle later on.
A response signal read out from the memory under test 200 is compared with a reference voltage supplied from the comparison reference voltage source 122 in the comparator 117, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a voltage of a predetermined logical H (logical high) or a voltage of a predetermined logical L (logical low). The response signal determined to have the predetermined logical level is sent to the logical comparator 115, where the response signal is compared with an expected value signal outputted from the pattern generator 112, and it is decided whether or not the memory under test 200 has outputted a normal response signal.
If the response signal does not coincide with the expected value signal, the memory cell of the memory under test 200, that has the address from which that response signal has been read out is determined to be in failure, and a failure signal (failure data) indicating that fact is generated from the logical comparator 115.
Usually, the failure analysis memory 118 has the same operation speed and storage capacity as those of the memory under test 200, and the same address signal as an address signal applied to the memory under test 200 is applied to the failure analysis memory 118. In addition, the failure analysis memory 118 is initialized prior to starting the testing. For example, by the initialization, a data of logical “0” is written in all of the addresses of the failure analysis memory 118. Each time a failure data representing the disagreement between the response signal and the expected value signal is generated from the logical comparator 115 during the testing of the memory under test 200, a failure data (for example, logical “1” data) indicating that the tested memory cell is in failure is written in the same address of the failure analysis memory 118 as that of the memory cell of the memory under test 200 from which the disagreement has occurred.
On the contrary, when the response signal coincides with the expected value signal, the memory cell of the memory under test 200 having the address from which the response signal has been read out is determined to be normal, and a pass signal indicating that fact is generated. This pass signal is usually not stored in the failure analysis memory 118.
At the time point when the testing has been completed, the failure data stored in the failure analysis memory 118 are read out therefrom into the failure repair analyzing and processing apparatus 120, and it is decided whether the failure memory cells of the tested IC memory 200 can be repaired or not. In general, in addition to the addresses of the failure memory cells of the memory under test 200, the test patterns given to those failure memory cells are also stored in the failure analysis memory 118, and at the time point when the testing has been completed, those data are read out from the failure analysis memory 118 into the failure repair analyzing and processing apparatus 119 in which it is decided whether the failure memory cells can be relieved or repaired or not.
Further, in FIG. 4, each of the driver 116 and the comparator 117 is illustrated by one symbol. However, in practice, the number of drivers 116 provided is equal to the number of input terminals of the memory under test 200, for example, if the number of input terminals is 512, then 512 of drivers 116 are provided, and the number of comparators 117 provided is equal to the number of output terminals of the memory under test 200 (since the number of input terminals provided is usually equal to the number of output terminals, the number of comparators 117 provided is equal to the number of drivers 116 provided). In addition, though each of the waveform formatter 114, the logical comparator 115, the failure analysis memory 118, the failure repair analyzing and processing apparatus 119, etc. is also shown by one block, the remaining elements except for the main controller 111 and the timing generator 112 are usually provided as many as the number of the drivers 116 (for example, 512).
The storage area of a semiconductor memory is generally divided into a plurality of storage regions, and each storage region is constituted of a large number of memory cells aligned along row address lines and column address lines, which is called a memory cell array in this technical field. In addition, each storage region (each memory cell array) is called a block. The storage capacity of a semiconductor memory is the sum value of the memory capacities of the plural memory cell arrays.
In case of a memory having redundancy structure, each of the storage regions is provided with a desired number of column spare lines and a desired number of row spare lines formed in the row address direction and in the column address direction respectively at the periphery of the memory cell array. Each column spare line includes the same number of memory cells as that of the column address lines in the memory cell array and each row spare line includes the same number of memory cells as that of the row address lines in the memory cell array.
In addition, in case of a multi-bit memory, a memory element constituted of the above-mentioned plural memory cell arrays (hereinafter, referred to as memory cell array group) is formed on the same semiconductor chip as many as the number of bits. A multi-bit memory having redundancy structure is shown in FIG. 7.
A memory 200 shown in FIG. 7 is an (N+1)-bit memory, and a bit-1 memory cell array group 201-0 that stores data corresponding to the first data bit (bit-0), a bit-2 memory cell array group 201-1 that stores data corresponding to the second data bit (bit-1), a bit-3 memory cell array group 201-2 that stores data corresponding to the third data bit (bit-2), . . . , a bit-N memory cell array group 201-N that stores data corresponding to the (N+1)th data bit (bit-N) are formed on the same wafer WH. That is, the same number of the memory cell array groups as that of bits of a multi-bit test pattern signal to be written in the memory 200 is formed on the same wafer WH. Though these memory cell array groups are shown in three dimensional manner in FIG. 7, they are, in practice, formed in planar manner.
A plurality of (six, in this example) memory cell arrays 202 are formed in the inside of each of the plural memory cell array groups 201-0, 201-1, 201-2, . . . . In addition, a desired number of column spare lines SC and a desired number of row spare lines SR are formed in the row address direction ROW and in the column address direction COL respectively at the periphery of each memory cell array 202. Further, in this example, a case is shown that two row spare lines SR are disposed along one side in the row address direction of each memory cell array 202 and two column spare lines SC are disposed along one side in the column address direction of each memory cell array 202. However, it is needless to say that the number of spare lines and the positions where these spare lines are disposed are not limited to the example as illustrated.
FIG. 5 is a block diagram showing a rough construction of the prior art failure repair analyzing and processing apparatus 119 that is used in testing a multi-bit IC memory such as the multi-bit IC memory shown in FIG. 7, and FIG. 6 is a block diagram showing a rough construction of the prior art failure analysis memory 118 that is used in testing a multi-bit IC memory.
As shown in FIG. 6, the failure analysis memory 118 comprises: a storage part AFM provided with a data input terminal Dn, an address input terminal An, a data output terminal Qn, etc.; an address selector for selecting and taking out an address signal PADR supplied from a pattern generator 112; and a multiplexer MUX having one input terminal A to which an address signal FADR supplied from the failure repair analyzing and processing apparatus 119 is applied and the other input terminal B to which an address signal supplied from the address selector ADS is applied, the multiplexer MUX selecting either one of the address signal FADR or the address signal PADR to output the selected one.
As shown in FIG. 5, the failure repair analyzing and processing apparatus 119 comprises: a control part 10 for outputting an analysis start signal ALSRT, a bit specifying signal BITSP, a load signal LOAD, etc.; and a repair analysis unit 20 that operates under the control of the control part 10.
The repair analysis unit 20 comprises: a bit specifying part 21 constituted by a bit specifying register 21A, a group of AND gates 21B and an OR gate 21C for performing a logical addition (OR) of the AND gate group 21B; a latch circuit 22 for temporarily storing data outputted from the bit specifying part 21; an operation and processing part 23 for performing an operation or computation of data read out from the latch circuit 22; a failure block memory 25 for storing a memory cell array from which a failure memory cell is detected; and an address generator 24 for generating an address signal for accessing an address of the failure analysis memory 118 in carrying out a repair analysis and processing. The repair analysis unit 20 starts a repair analyzing operation when it receives an analysis start signal ALSRT from the control part 10, and sends an analysis end signal ALEND to the control part 10 when the repair analyzing operation for one data bit (one memory cell array group) is completed.
Into the bit specifying register 21A is loaded a bit specifying signal BITSP being applied to the data terminal thereof when a load signal LOAD is applied thereto from the control part 10, and the register 21A specifies one data bit (one of the memory cell array groups) of the memory under test 200 that a repair analysis and processing should be performed. In reality, it specifies the data bit memory area of the failure analysis memory 118 in which failure data existing in one data bit (one memory cell array group) of the memory under test 200 have been stored. Each AND gate of the AND gate group 21B has two input terminals, and a bit specifying signal BITSP from the bit specifying register 21A is applied to one input terminal of each AND gate and a failure data FAIL read out from the data output terminal Qn of the failure analysis memory 118 is sequentially applied to the other input terminal of each AND gate. Accordingly, the AND gate group 21B has the same number of AND gates provided therein as that of the data bits (the memory cell array groups) of the memory under test 200, and only one AND gate corresponding to a bit specifying signal BITSP from the bit specifying register 21A is enabled.
During the testing of the memory under test 200, the multiplexer MUX of the failure analysis memory 118 selects the other input terminal B so that the multiplexer MUX supplies address signals PADR to the address input terminal An of the storage part AFM, the address signals PADR being supplied to the other input terminal B from the pattern generator 112 through the address selector ADS. As a result, each time the disagreement occurs in the logical comparator 115, a failure data FAIL applied to the data input terminal Dn of the storage part AFM will be stored in the same address of the storage part AFM as that of the failure memory cell of the memory under test 200 from which that disagreement has occurred.
Further, in the specification, “failure data” means data that, in case the memory under test 200 is a multi-bit memory, has the same bit width as that of data read out from this memory under test 200 as well as all bits thereof are logical “0” where no disagreement occur in the logical comparator 115, and where one or more disagreements occur in the logical comparator 115, only one or more bits of the data from which the one or more disagreements have occurred are changed to logical “1”. For example, in case the memory under test 200 is an eight-bit memory and is constituted of eight data bits (memory cell array groups), data of eight bits from data bit 1 to data bit 8 is written in the memory under test 200. Accordingly, where no disagreement occurs in the logical comparator 115, the failure data becomes a data of “00000000” in which all of the eight bits are logical “0”. Where a disagreement is detected in the data bit 2, the failure data becomes a data of “01000000”, and where a disagreement is detected in both the data bit 3 and the data bit 6, the failure data becomes a data of “00100100”. Therefore, if such failure data are stored in the same addresses of the failure analysis memory 118 as the addresses of the memory under test 200 from which those failures have occurred, the failure occurrence addresses of the memory under test 200 and the locations or positions of those failure memory cells can be stored.
When the testing of the memory under test 200 has been completed, a failure repair analysis and processing of the tested memory 200 is carried out. The multiplexer MUX of the failure analysis memory 118 selects its one input terminal A so that it applies address signals FADR sent to the one input terminal A from the address generator 24 shown in FIG. 5 of the failure repair analyzing and processing apparatus 119 to the address input terminal An of the storage part AFM, thereby to access the failure data stored in the storage part AFM.
The failure data FAIL read out from the data output terminal Qn of the storage part AFM are supplied, in sequence, to the other input terminals of the AND gate group 21B of the bit specifying part 21 of the failure repair analyzing and processing apparatus 119. Since the bit specifying register 21A controls to enable only one AND gate in the AND gate group 21B corresponding to one data bit specified by the register, only the failure data (failure data of one bit) existing in the memory area of the specified data bit (memory cell array group) among the failure data FAIL read out from the storage part AFM are taken out into the latch circuit 22.
The failure data of one bit taken out into the latch circuit 22 are recognized as to in which memory cell array 202 and on which address line of the recognized memory cell array they exist on the basis of address signals generated from the address generator 24, and further, the location (address) of the failure memory cell on that recognized address line is specified and is sent to the operation and processing part 23. The operation and processing part 23 adds up in number the failure data taken therein in each address line for each memory cell array 202, and operates or computes and processes as to whether the address line on which one or more failure memory cells exist can be repaired by use of spare lines SC, SR provided on each memory cell array 202.
Moreover, the operation and processing part 23 reads out the stored data in the failure block memory 25 therefrom, and if there is a memory cell array from which any failure memory cell has not been detected, the operation and processing part 23 controls such that the address generator 24 does not generate an address signal to access the memory cell array from which any failure memory cell has not been detected and generates an address signal to access a subsequent memory cell array to be analyzed and processed next time from which a failure memory cell or cells have been detected. That is, the repair analysis and processing for each of memory cell arrays from which no failure memory cell has been detected is not carried out and the repair analysis and processing for a subsequent memory cell array to be analyzed and processed next time is executed at once.
In the prior art failure repair analyzing and processing method described above, failure data in a data bit (memory cell array group) specified by the bit specifying part 21 are read out one bit by one bit using address signals and are sent to the operation and processing part 23. Specifically explaining, in case of a multi-bit memory under test 200 shown in FIG. 7, a plurality of memory cell array groups 201-0, 201-1, 201-2, . . . , 201-N are specified one memory cell array group by one memory cell array group by the bit specifying part 21, and the repair analysis and processing for (N+1) memory cell array groups 201-0, 201-1, 201-2, . . . , 201-N is carried out one group by one group. Accordingly, there is a disadvantage that a time required to execute the repair analysis and processing for (N+1) memory cell array groups comes to considerably long.
Furthermore, in case of testing a large number of multi-bit memories each having redundancy structure at the same time, the failure analysis memory 118 shown in FIG. 6 and the failure repair analyzing and processing apparatus 119 shown in FIG. 5 are provided for each memory under test. These large number of the failure analysis memories 118 and the failure repair analyzing and processing apparatuses 119 are concurrently operated in parallel with one another so that the failure repair analysis and processing for each of the large number of memories under test is carried out.
In such case, a failure repair analyzing and processing apparatus that executes the failure repair analysis and processing for a memory under test in which many failure memory cells exist becomes naturally long in its processing time, and hence the processing speed thereof is lowered. As a result, in case the failure repair analysis and processing for each of the remaining memories under test has been completed, the failure repair analyzing and processing apparatuses that have completed the failure repair analysis and processing are stopped to operate, and the failure repair analysis and processing for a memory under test in which many failure memory cells exist is continued in the state that the failure repair analyzing and processing apparatuses that have completed the failure repair analysis and processing are waiting on. Accordingly, even there exists only one failure repair analyzing and processing apparatus that takes a long time to carry out the failure repair analysis and processing for a memory under test, the failure repair analysis and processing time for the whole apparatuses comes to the failure repair analysis and processing time for the failure repair analyzing and processing apparatus that has taken the longest time, which results in a shortcoming that the failure repair analysis and processing cannot be carried out at high speed.
Recently, since the storage capacity of a memory is increasing more and more and the number of bits of a memory is also increasing, there has been a tendency that the failure repair analysis and processing time for a memory having redundancy structure is still more increased. For this reason, it is strongly demanded that the failure repair analysis and processing can be performed at high speed.